Over the years it has become standard practice to use a stable and accurate low-frequency clock or frame pulse (also referred to as a low-frequency sync) to periodically adjust the phase of synchronized devices and equipment locked to a high frequency reference. The high-frequency reference clock could be, for example, a T1 reference (1.544 MHz) up to say 156.25 MHz, whereas the low frequency clock could be from say 1 Hz, for example, in the case of a GPS signal, to an 8 KHz framing pulse.
In order to use such a clock as a reference for a PLL, and to guarantee proper PLL response and overall stability, the bandwidth of such a PLL has to be at least an order of magnitude lower than that of the low-frequency clock. Such a low bandwidth implies an unacceptably long time to align with the phase of the low-frequency clock.
For applications where a high-frequency clock can be traced to the same primary reference source as the low-frequency sync, it is possible to let the PLL lock to the high-frequency clock using a relatively high bandwidth, and provide the low-frequency sync as an additional synchronization source. In this mode, the PLL outputs are locked in both phase and frequency to the high-frequency clock. The phase of the PLL output can be periodically adjusted to be aligned with the low-frequency clock. Typically, the PLL outputs are aligned to the high-frequency clock edge, nearest to the low-frequency sync edge as shown in FIG. 1.
In the prior art, two methods are known for achieving PLL output clock alignment to a low-frequency sync reference. A first method (referred herein to as the hybrid method) a Numerically Controlled Oscillator (NCO) is used in combination with a regular PLL locked to a high-frequency reference. This method requires a device to represent the low-frequency sync by a numerical word that is used to control the NCO such that the PLL output clocks are aligned to the low-frequency sync. This method also requires the ability to switch between the NCO and regular PLL locking modes.
FIG. 2 is a block diagram of such a hybrid method, showing the external PLL, which achieves phase alignment with the sync through NCO control and the regular PLL, which then achieves alignment with the reference.
The disadvantages of this method are complexity and high cost of implementation (due to the requirement of extracting the low-frequency sync phase, and switching between the locking modes), and the lack of a mechanism that can perform automatic phase adjustments when the low-frequency sync is disrupted or changes phase. Phase jumps at the output of the PLL, when switching between NCO and PLL regular locking mode, are also a common problem with this method.
A second method, shown in FIGS. 3 and 4 involves sampling the low-frequency sync using a high-frequency reference clock and making the output phase adjustments based on the sampled phase difference.
The Sync Control block can functionally be represented as a block that allows sampling of the low-frequency sync by a high-frequency reference clock and gating the high-frequency reference clock or the low-frequency feedback clock, therefore allowing the Phase Detector block to measure phase difference between the low-frequency sync and the low-frequency feedback clock.
Although this method is simpler than the hybrid method, it lacks flexibility and ease of application. It also requires complicated logic. The main disadvantage of this method however is its inflexibility due to its nature of sampling low-frequency sync using a high-frequency reference. In order to guarantee proper sampling, the edge of the low-frequency sync must not coincide with the high-frequency reference edge. The low-frequency sync must actually lag the high-frequency reference. This is particularly hard to guarantee since both the high-frequency clock and the low-frequency sync must be traceable to the same primary reference source. In addition, the difference in nominal frequency between the two can be significant, such that the high-frequency clock is required to be routed using differential pins, whereas the low-frequency sync is delivered using standard single-ended pins. In almost all cases, the customer is required to use additional hardware to ensure that the sync pulse is sampled with an opposite high-frequency clock edge than the one used in the PLL, prior to being sent to the synchronizing PLL.
Another disadvantage with this method is the inability to automatically perform periodic realignment of the PLL output clocks with the low-frequency sync. In an environment where wander and jitter are present, if an error is made with the initial measurement, a misalignment is introduced between the output clocks and the low-frequency sync, and the error remains in the system.